ScanWorks® Platform for Embedded Instruments

Several standards are relevant to validation and test using instruments embedded on-chip.

IJTAG (IEEE 1687)

The official name for the preliminary IEEE P1687 Internal JTAG (IJTAG) standard is IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device. (Ratification of the standard is expected in 2011.) Since the IEEE P1687 standard makes use of the IEEE 1149.1 boundary scan or JTAG standard as an enabling technology, it is usually referred to as IJTAG.

IJTAG standardizes the interface to instruments embedded in chips and defines a methodology for accessing and automating their operations, and analyzing their output. The IEEE P1687 IJTAG standard defines two languages, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the connections among embedded instruments in chips and on circuit boards while PDL is an extension of the popular Tcl (Tool command language) for programming validation, test and debug vectors to be executed by IJTAG instruments.

Here’s a link to the IEEE web site where you’ll find more information on IJTAG technology.

http://grouper.ieee.org/groups/1687/ 

IEEE 1500

The IEEE 1500 Standard for Embedded Core Test was developed to facilitate the testing and integration of embedded cores into system-on-a-chip (SoC) devices and other complex semiconductor components. It enables test reuse from one chip to another.

IEEE 1500 defines serial and parallel Test Access Mechanisms (TAMs) and a rich set of instructions. Its Core Test Language (CTL) is the mechanism for describing IEEE 1500 wrappers and the test data associated with the core under test.

Here’s a link to the IEEE web site where you’ll find more information on IEEE 1500 technology.

http://grouper.ieee.org/groups/1500/

IEEE 1149.7

Ratified late in 2009, the IEEE 1149.7 standard maintains compatibility with the original IEEE 1149.1 boundary-scan standard while reducing the number of device pins required from four to two. In addition, IEEE 1149.7 includes enhanced test functionality for the purposes of testing and characterizing complex chips, such as SoCs, multi-die chips, 3D chips and multi-chip modules.

One of the enhancements to IEEE 1149.7 is the inclusion of a star topology to complement the standard serial topology supported by IEEE 1149.1. Because of the star topology, designers can more easily manage multi-die architectures since the physical inter-device connections are greatly simplified.

Here’s a link to the IEEE web site where you’ll find more information on IEEE 1149.7 technology.

http://grouper.ieee.org/groups/1149/7/

Resources…

IEEE 1687 IJTAG Tutorial
Learn more about the implementation of IEEE 1687 IJTAG to access and control embedded instruments in this informative tutorial by Al Crouch, ASSET’s chief technologist for core instrumentation and vice chairman of the IEEE IJTAG working group.

IEEE 1687 IJTAG
Click here for a blog post, “What is IEEE 1687?” by Al Crouch, ASSET’s chief technologist for core instrumentation and vice chairman of the IEEE IJTAG working group.

Click here for another blog post, “Who will use IEEE 1687?” by Al Crouch, ASSET’s chief technologist for core instrumentation and vice chairman of the IEEE IJTAG working group.

IEEE 1149.7
Click here for a technical paper presented at the International Test Conference (ITC) by Adam Ley, ASSET’s chief technologist for boundary scan. “Doing more with less – An IEEE 1149.7 Embedded Tutorial”.

For more information on any of the other technologies supported by the ScanWorks platform, click one of the following links:

• What is Embedded Instrumentation?
• JTAG (IEEE 1149.x)
• Processor Debug Ports
• I/O Instrumentation
• Intel® IBIST

Find out what value IJTAG would provide in your own chip and board designs.