ScanWorks® Platform for Embedded Instruments

JTAG or Boundary Scan

Generally speaking, JTAG refers to an implementation of the technology described in the IEEE 1149.1 Boundary-Scan Standard. This standard is often referred to as JTAG after the Joint Test Action Group, which initiated the development of the specification before it became an official standard of the IEEE.

In a more specific way, JTAG is often associated with the port on a processor that implements the IEEE 1149.1 boundary scan interface or Test Access Port (TAP). This interface is often called the JTAG port. It is commonly used for a number of purposes, including structural board test, on-board flash memory programming and CPLD/FPGA configuration, memory testing and others.

IEEE 1149.1 Test Access Port (TAP) and Boundary-Scan Architecture (JTAG)

IEEE 1149.1 Boundary-Scan Standard (JTAG) was developed during the 1990s. Boundary scan came about as a non-intrusive board test technology in response to several developments. Fine-pitch pins on chips and chip-scale packages with the pins underneath the silicon die could not be probed by intrusive test technologies like in-circuit test (ICT) equipment, flying probe test and manufacturing defect analyzers (MDA). Moreover, many circuit boards could not accommodate the test pads that had been essential to intrusive test technologies. Instead, JTAG or boundary-scan tests are applied to a circuit board through a connector and the four-wire TAP interface.

Since the 1990s, the original IEEE 1149.1 boundary-scan standard has spawned a family of related standards.

Here’s a link to the IEEE web site with information on the IEEE 1149.1 standard, click here.

IEEE 1149.6 Boundary-Scan Standard for Advanced Digital Networks

Based on the groundwork laid by the IEEE 1149.1 boundary-scan standard, the IEEE 1149.6 specification defines test methodologies for high-speed buses in the one to 10 gigabits-per-second (Gbps) range that feature serial AC-coupled chip-to-chip interconnects and/or differential signaling, such as Gigabit Ethernet, Fibre Channel and others. Typically, IEEE 1149.1 boundary scan only tests the DC-coupled device networks on a circuit board.

Here’s a link to the IEEE web site with information on the IEEE 1149.6 standard, click here.

IEEE 1149.7 Standard for Reduced-Pin and Enhanced Functionality Test Access Port (TAP) and Boundary-Scan Architecture

Ratified by the IEEE in 2009, the IEEE 1149.7 standard is backward compatible with the original IEEE 1149.1 standard, but this newer standard offers options for a smaller, two-wire interface and enhanced functionality. IEEE 1149.7 extends the test and debug capabilities of the IEEE 1149.1 TAP to complex devices like system-on-chip (SOC), system-in-package (SIP) and other multi-core or multi-die devices.

"Doing More with Less – An IEEE 1149.7 Embedded Tutorial": an in-depth, illustrated explanation of IEEE 1149.7, presented at the International Test Conference by Adam W Ley, Chief Technologist at ASSET InterTech, and chief author of the test content in the draft 1149.7 standard.

Here’s a link to the IEEE web site with information on the IEEE 1149.7 standard, click here.

IEEE 1532 Standard for Boundary-Scan-Based In-System Configuration of Programmable Devices

The IEEE 1532 standard uses the IEEE 1149.1 boundary scan standard as an underlying technology to define an open and standardized method for programming logic devices after they have been assembled onto a printed circuit board. The standard also specifies concurrent programming capabilities which allow more than one programmable device to be simultaneously configured in-system.

Here’s a link to the IEEE web site with information on the IEEE 1532 standard, click here.

Other resources:

For a free handbook explaining IEEE 1149.1 boundary-scan test and its many benefits, click here. (Registration required.)

For more information on the many benefits manufacturers derive from boundary scan, click here.

For more information on any of the other technologies supported by the ScanWorks platform, click one of the following links:

• What is Embedded Instrumentation?
• Processor Debug Ports
• I/O Instrumentation
• Intel® IBIST
• IJTAG (IEEE 1687)

Ask us why JTAG running on the ScanWorks Platform is the most versatile solution for your board designs.