Processor-Controlled Test (PCT) Debug Port Access

ASSET InterTech's Boundary-Scan Test, Processor-Controlled Test and I/O Instrumentation for Intel® IBIST are unique tools for access, automation and analysis of embedded instrumentation.

Connecting To Your Boards

PCT Product Selector

Processor-Controlled Test (PCT) only needs 5-10 test points to access the board under test.

Methods of connection to the board under test

PCT can combine both CPU Emulation and JTAG test methods. The connection of the Test Interface POD(s) is determined by which of these test methods is being used and also the architecture of the board.

CPU Emulation Tests

To carry out CPU Emulation, PCT needs to access the processor's debug port. This access is achieved either via a CPU-dedicated JTAG connection, or via a common JTAG port where the CPU is one of the components in the scan chain. The connection options are:

An on-board JTAG header - many manufacturers include separate on-board JTAG headers for general scan chain and processor-only scan chain. Two types of header are illustrated.

An interposer can be used for socketed processors if no on-board JTAG header is available. This is a small PCB with a built-in JTAG header that fits between the processor and its socket.

A simple fixture with 5-10 probes to contact JTAG lines from the processor. This method is required if methods 1 and 2 are not possible.

What is a Processor Debug Interface?

When PCT performs CPU Emulation it accesses the board under test via the processor's debug port. This requires only 5-10 accessible test points - ideal for accessing densely packed boards and minimizing board stress.

The embedded hardware and software debug features of the debug interface were originally provided by processor manufacturers to assist board designers. The debug interface provides access to traditional processor emulator features such as: