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PRODUCTS

BSDL Services:
BSDL Validation Service
ScanWorks®
Boundary-Scan Products:

Interconnect Development Station
Interconnect Repair Station
Test Development Station
Diagnostic & Repair Station
Manufacturing Station
Programming Stations
IEEE 1149.6
Emergency License Tokens
Hardware Overview

IBIST Products:
ScanWorks® Intel® IBIST
Emulation Products:
MicroMaster
ICT Products:
ScanWorks® for Agilent's Medalist ICT
Technology:
Test Automation
System-Level JTAG


 

ScanWorks® JTAG Test Development Station Bundle

Memory Access Verification

ScanWorks’ Memory Access Verification feature can dramatically increase test coverage by generating tests that verify the connections between memory chips and boundary-scan devices. Memory devices are very often connected to a processor, PLD or ASIC-based memory controller, which usually include boundary-scan functionality. Tests based on a device’s boundary-scan description language (BSDL) file and a memory device models are automatically generated to write data to and read data from memory devices, adding opens coverage to the shorts coverage provided by interconnect tests. Memory models for most memory types, including SRAM, DRAM, SDRAM, DDRAM and others are provided on ASSET’s web site to maintenance customers only.

ScanWorks automatically detects access to memory devices and tests are generated that detect and diagnose defects on the memory devices data, address and control signals. An interactive debugger is built into ScanWorks to simplify the debug process. For details on Memory Access Verification see the Memory Access Verification Fact Sheet on the ASSET web site.

Features

Several capabilities of the ScanWorks Test Development Station increase test coverage or improve the efficiency of test generation and deployment to manufacturing.

Comprehensive Fault Coverage Report

ScanWorks generates a comprehensive fault coverage report so you can easily identify the test coverage afforded by all of the tests that may be applied to a board. Because you may not always apply all of the test actions, the report generator allows you to select the test actions that will be included in the report. Any coverage resulting from a Scan Path Verify, Interconnect, Memory Access Verification or Flash programming action is included in the report. Any coverage obtained by using the IEEE 1149.6 High-Speed Interface Testing feature is also included in the report. The report specifies the number and percentage of pins with full, partial or no test coverage. Pins with full, partial or no shorts coverage and devices with full, partial or no opens coverage down are also reported.

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