ScanWorks® JTAG Test Development Station Bundle

Describing Your Design

ScanWorks builds a description of your design from various types of information, including Boundary Scan Description Language (BSDL) files, CAD files of the design and models of non-boundary-scan devices. BSDL files are the only required files, but when more information is provided, such as CAD data and devices models, tests can be developed and deployed much faster. Many BSDL files, flash memory models, dynamic memory models and non-boundary-scan device models are available on ASSET’s web-based model library available to maintenance customers only.

ScanWorks provides two methods for describing your design. If you know the boundary-scan devices and their order on the scan path, it is easy to list them in the proper order and to assign the proper BSDL file to each device. ScanWorks then automatically builds the required description files from this list. If the design is large or you don’t have the CAD files, the ScanWorks Scan Path Discovery utility can take a netlist and automatically discover the devices on the scan path, determine their order on the path, create description files and a block diagram of the scan path, and generate scan path verification tests. ScanWorks will accept practically any netlist format. Netlists are imported and converted to the ScanWorks’ internal format.

ScanWorks also uses non-boundary-scan device information to ensure that any tests of the connections between boundary scan (JTAG) and non-boundary scan (JTAG) devices will be safe for the board. ScanWorks will not test any net if it is not certain that the test will be safe for the board. Device models describe non-boundary-scan devices’ IO characteristics. Many of the most common device models are available to ScanWorks users under maintenance contracts from ASSET’s web-based model library. If a model is not available, it can be readily created.

ScanWorks supports the description of more than one scan path in a design, and provides optional hardware to connect to more than one scan path. See the Multiple Scan Path support section of this document.

Creating Tests

Test creation in ScanWorks is semi-automated. Each type of test is organized as an “action”. The different types of tests include scan path verification, interconnect tests, PLD programming, I2C programming, custom tests using ScanWorks macros and Boundary Scan Language (BSL) files, tests generated with Serial Vector Format (SVF), plus the optional memory access verification and flash programming operations. Multiple actions of each type can be created and saved for each design.

Each action is created through an intuitive user interface designed specifically for that action. The organization and format of the dialog box is consistent across all actions, making them easy to learn and use. Because most of the information needed to create a test is already available in the design description, the initial test can usually be built with one click of a button. Report logs indicate any errors or warnings that must be resolved. The test developer is given options to modify the test for increased coverage or to adjust the test for special circumstances. ScanWorks’ test coverage reports help you determine where additional coverage is needed and how to extend coverage to these areas. Also, tests can be applied directly from the development dialog so they can be validated rapidly against the hardware. You can also set preconditions to initialize your design for testing. And if more than one scan path is present on a board, you can select the scan path for testing. For more information on each test type refer to the detailed descriptions below.

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