ScanWorks^® JTAG PLD Program Generation

Product Overview

In-system configuration (ISC) of programmable logic devices (PLD) has evolved into a major application of boundary-scan technology. The benefits of ISC enable you to reduce time to market and cut production costs. ISC easily can be integrated with your existing ScanWorks® station, set up as an ISC-only station, or combined with the ScanWorks flash programming tools. The PLD Program Generation option can be added to a Programming Station, a Test Development Station, or to a Diagnostic & Repair Station.

ISC is supported in most PLDs by providing access to internal programming registers through an IEEE 1149.1-compliant Test Access Port (TAP). Using the IEEE 1149.1 TAP takes advantage of a well-established standard serial interface that already exists on most PLDs. ISC also allows tools created for boundary-scan-based testing to be easily adapted to support ISC. ScanWorks ISC programming support is based on the concept that the PLD vendors are best able to create programming files that contain the data to be loaded and the algorithm needed to load it. ScanWorks supports file formats used by the PLD vendors and makes it easy to import and apply the files.

ScanWorks Supports All Boundary-Scan (JTAG) Configurable PLDs

PLDs can be classified in two major categories ― complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs generally use non-volatile technology while FPGAs are volatile and must be reconfigured at power up. Almost all CPLDs released recently by Altera, Xilinx (including former Philips devices), Lattice (including former Vantis devices), Cypress, and Atmel can be configured in-system with JTAG (boundary scan). These vendors provide over 98% of the CPLDs sold. Most FPGAs can be configured in-system with JTAG, but some have features that are not fully compliant with IEEE 1149.1 operations, making programming with boundary-scan impossible. ScanWorks supports all devices that can be configured with boundary scan (JTAG). Visit the ASSET web site for a current list of supported devices.

PLD Programming Files

All PLDs with JTAG (boundary scan) can be configured using one of two file formats. Altera, Xilinx, and Lattice use the serial vector format (SVF), and Altera and Cypress use the JEDEC Standard Test and Programming Language (STAPL).

SVF is a vector exchange format, designed to enable transfer of boundary-scan vectors between tools. SVF is a vector format, not a programming language and does not support flow control within the language. When executed, the entire contents of the file are applied and all included operations are accomplished. In some cases, separate files are needed for erase and programming operations. SVF supports the delay periods needed by PLDs to complete the write operations. SVF is applied quickly for fast programming times, but large devices require large programming files.

STAPL is a JEDEC standard programming language and can support adaptive programming and flow control. Typically, one file contains the procedures for all supported operations. When executed, specific operations can be requested and only the requested operations are accomplished. STAPL also supports delay periods needed for programming. The JEDEC version of STAPL is an interpreted language that is slower than SVF, but Altera provides a compiler to reduce file size and programming time by 3-5X. ScanWorks supports both the interpreted and compiled versions of STAPL.

PLD Programming Applications

PLD programming is supported in ScanWorks by SVF and STAPL actions. Within these actions, you select the target PLD to be programmed and the file used to program the PLD. Once the inputs are specified, the test is built, creating the application files. SVF source files are translated to a binary format and STAPL source files are complied. Either format can be applied in the ScanWorks environment to verify it works correctly and to diagnose problems.

Once the operation is verified to work, the tests can be added to a ScanWorks sequence or executed from a custom user interface created with the API provided with all ScanWorks applications. The PLD actions are executed exactly like test actions, making integration of test and ISC a seamless operation.

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