ScanWorks^® JTAG Net List Merging

Product Overview

ScanWorks netlist merging feature enables the creation of tests that span more than one printed circuit board (PCB). By combining or merging the netlist of two or more PCBs, boundary-scan tests can be created as if one PCB is being tested. The connection between the PCBs are tested, verifying the connections between boundary-scan devices and the PCB connectors are good and verifying that the connectors are properly mated together. This concept is very useful for testing motherboard/daughter board assemblies and to verify PCBs are properly installed in a back plane. It is also used to describe the connections between your PCB and the ScanWorks BSIO-400 Parallel IO Module.

A merged netlist is created at the design level and it is used for any action that requires a netlist, such as interconnect ATPG, scan path verification, memory access verification, and flash programming. The netlist merging feature allows you to do some preprocessing of the netlist to avoid repeating the process for each action you create. You can:

• Specify devices that are of device type “Dummy”, indicating they have no effect on scan path testing. Examples are bypass capacitors and test points.
• Identify power and ground nets
• Specify devices that are of type “Resistor” enabling the interconnect ATPG software to automatically determine the resistors that act as pull-ups, pull downs, and as transparent devices that can be tested through.

With the netlist merging feature you can specify individual device or connector pins to be merged, nets to be merged, or you can specify that all pins of two connectors be to be merged together.

Using the Net List Merging Feature

The netlist merging feature works at the design level, creating a netlist for a design that includes the PCB assemblies to be tested together. The scan path description for the design must include the devices in the scan chains for all PCBs being tested together.

The procedure for merging netlist starts with the netlists for the PCBs to be tested together. The netlists are imported into ScanWorks and translated into the internal ScanWorks format. A command file is created that specifies the pins, nets, or connectors to be merged together. It also specifies a header to be added to the pins, nets, or connectors of each PCB to make sure they have unique identifiers and can be identified to the correct PCB during fault isolation. A command file template is provided to ease the creation process. A user interface is provided to allow you to select the netlists to be merged and the command file to be used to merge them. See Figure 1.

The merging process occurs very quickly with even the largest designs, requiring only a few minutes of processing.

Once the netlist merging process is complete, any action that requires a netlist can be created with no extra steps. Pins and nets are identified with the prefix assigned during merging so that you always know the PCB on which the device pin or net is located.

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