ScanWorks® JTAG Model-Based Interconnect Tests 

Model-Based Interconnect Tests

Three types of data are needed to quickly generate safe board tests with high fault coverage:

• An accurate description of the boundary-scan features of the board
• An accurate description of the connections between devices on the board
• Information about the IO characteristics of all devices on the board that interact with any boundary-scan devices

The first two types of data were discussed above. The third type is derived from models of non-boundary-scan devices. Although ScanWorks does not need models of non-boundary scan devices to generate a test, tests are generated faster and with less manual intervention when ScanWorks has them.

ScanWorks interconnect test generation will not attempt to drive any net (node) for which it does not have enough information to determine whether another device is simultaneously driving the net (signal contention). Since many boundary-scan nets are also connected to non-boundary-scan devices, information about non-boundary-scan devices is needed to automatically create safe tests with high fault coverage. This information can be added manually by defining constraints.

Cluster models contain information on non-boundary-scan devices. Cluster models can describe the devices’ IO characteristics and certain basic logic functions. ScanWorks uses the logical descriptions contained in cluster models to determine whether test signals can be sent by an adjacent boundary-scan driver through a non-boundary-scan device to a boundary-scan receiver. This feature can dramatically increase test coverage. For a detailed description of how models are used to reduce test generation time while safely increasing test coverage, ask about our white paper on “Device Modeling is Critical for Fast Time-To-Test”.

Models can be automatically included into ScanWorks tests if strict naming conventions are followed during the design capture process or they can be added manually. Thousands of non-boundary-scan device models are stored in ASSET’s web-based model library, which is available to maintenance customers. Models can also be easily created or modified.

ScanWorks also provides many other useful features for interconnect test generation. For example, a visual user interface simplifies the creation of test constraints to prevent toggling of specific nets or pins. And to minimize ground bounce, parameters can be set to limit the number of pins or nets that toggle during any scan. Test coverage reports clearly identify the coverage at the net and pin level. Nets are classified according to coverage and reported as a percentage of coverage in each class. An interactive debugger gives you a view of the vector as it is applied. The optional IEEE 1149.6 High-Speed Interface Testing feature adds the ability to test AC-coupled/differential signaling connections between devices. See the description below for more information about IEEE 1149.6 testing.

Net-level and pin-level diagnostics are included in the Test Development Station. To rapidly isolate defects, the Graphical Fault Highlighting feature links a pin or a net from a fault report to a graphical view of the board layout. For details on interconnect testing see the Interconnect Test Fact Sheet on the ASSET web site.

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