ScanWorks^® JTAG Memory Access Verification

Fault Coverage

The memory interconnect software detects the following types of faults:

• Address bus stuck-at faults
• Data bus stuck-at faults
• Control line pass/fail
• Address bus open faults
• Data bus open faults
• Bridging faults on address and data lines

Test Application

Once successfully built, memory access verification test vectors are applied to your unit being tested through either the test development user interface, as a test step in the ScanWorks sequencer, or through one of several APIs provided with ScanWorks. (See ScanWorks APIs document) Test results are diagnosed in the same operations the application and are written to a log file.

Fault Diagnosis

Following vector application, the standard diagnostic report provides greater flexibility to better isolate the interconnect faults. ScanWorks provides a diagnostic report in HTML format that provides a diagnosis of the detected fault to the data or address net. It displays the net name along with the memory device and pin of the failing net. Select the pin name in the report and the design browser displays the layout view of the design with the location of the pin indicated by cross hairs. The design browser provides access to all available information about the design.

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