ScanWorks^® JTAG Memory Access Verification

Product Overview

ScanWorks Memory Access Verification automates the test generation for interconnects between boundary-scan components and associated memory components that do not contain boundary scan (JTAG). Including vectors to verify the integrity of the address, control, and data lines for on-board memories can significantly improve the test coverage available with boundary-scan and reduce the need for physical test points. The results are less complex in-circuit test fixtures and tests, with significant savings in cost of test.

What is a Memory Cluster?

A memory cluster is a group of physical memory on a printed circuit board whose interface can be accessed and controlled from adjacent boundary-scan devices. A cluster must have the address, data, and control lines in common to be tested as a cluster.

Test Vector Creation

The memory access verification software uses information available in netlists and memory device models to automatically determine the boundary-scan capable pins to be used to access the memory cluster. If any memory signal cannot be automatically associated with a boundary-scan pin, an easy-to-use node browser enables you to specify the boundary-scan pin to be used. The automatic test pattern generation tools generate patterns to detect opens, shorts, and bridging faults based on the read/write protocol in the memory models. The user can select options to test control signals, Wagner counting patterns for fault detection, and/or walking 1’s and 0’s patterns for better diagnostics. The resulting vectors provide a complete and compact set of vectors for testing all memory cluster interface lines. An additional option creates patterns to test the memory cells. These patterns write to and read from every memory cell within a specific range, providing a complete test of the memory cluster.

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