ScanWorks^® JTAG Interconnect Development Station Bundle

Interconnect Development Station Options

Several options to the ScanWorks Interconnect Development Station will increase test coverage or improve the efficiency of test generation and deployment to manufacturing.

Memory Access Verification

Memory devices are very often connected to a processor, PLD or ASIC-based memory controller. Almost all processors, PLDs and ASICs include boundary-scan functionality. The Memory Access Verification option of ScanWorks can dramatically increase the test coverage on your board by generating tests that verify the connections between memory and boundary-scan devices. Tests based on a device’s boundary-scan description language (BSDL) file and memory device models are automatically generated. Memory models for most memory types, including SRAM, DRAM, SDRAM, DDRAM and others are provided on ASSET’s web site.

ScanWorks automatically detects access to memory devices and tests are generated that detect and diagnose defects on the data, address and control signals. An interactive debugger is built into the tool to simplify debugging test problems and board defects.

For details on Memory Access Verification see the Memory Access Verification fact sheet on the ASSET web site.

Design Browser

The Design Browser provides many benefits. First, it provides a direct link between CAD tools and ScanWorks’ test generation tools. In addition, test engineers have access to all design data in an easy-to-use interface without having to learn how to use the CAD tools. Testability comments can be annotated in the files and returned to designers for review. Design changes can be immediately communicated to test engineers. In addition to the link between design and test, the Design Browser extracts interconnect information (netlist) that’s needed for test generation and then displays the location of faults in either a layout or schematic view.

For details on Design Browser see the Design Browser fact sheet on the ASSET web site.

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