ScanWorks^® JTAG Interconnect Development Station Bundle

Custom Test Generation

Although most boundary-scan interconnect tests can be developed with ScanWorks’ automatic test pattern generation (ATPG) tools, many times additional coverage can be achieved by manually generating tests. This is especially useful when a boundary-scan test can observe patterns applied to non-boundary-scan logic or analog circuits. JTAG or boundary scan often is used during prototype debug or board repair to set static conditions on a board to initialize it for other types of tests such as probing with other instruments. A convenient way to create custom tests or to apply specific boundary-scan patterns to a PCB is to use the ScanWorks’ macro programming language.

The ScanWorks Interconnect Development Station’s macro programming language is a powerful, high-level language that provides access to your design at any level; including individual scan cells, entire test registers or subsets of test registers. With specialized functions and procedures you can control or observe a specific pin or create a complete test for a cluster of non-boundary-scan logic. With a macro program you can establish “safe” conditions before entering the boundary-scan test mode or maintain a safe state throughout testing.

Another option for custom testing is the Boundary scan Stimuli Language (BSL). A BSL action can easily test a cluster of non-boundary-scan logic. BSL can automatically create a template file that specifies the boundary-scan pins that control and observe the non-boundary-scan logic. You then fill the file with the vectors that will be applied to test the logic cluster.

Tests in Serial Vector Format (SVF) can also be imported from other test generation tools. SVF is the de facto standard for transporting boundary-scan tests among tester systems. While SVF is convenient, it is limited in the diagnostic information it provides. In addition, imported SVF files are applied “as is” without the normal safeguards that are built into ScanWorks’ actions.

PLD (Programmable Logic Device) Programming

Strictly speaking, PLD programming is a test operation. This is another very useful feature of a ScanWorks Interconnect Development Station. Most PLDs, including CPLDs and FPGAs, can be programmed through the JTAG pins on the device. Tools from PLD vendors such as Xilinx, Lattice, Altera and Cypress create programming files in either SVF or in Serial Test And Programming Language (STAPL) (sometimes referred to as JAM files). ScanWorks imports these files and manages the scan path on which the device to be programmed is located. The target device can be located on any accessible scan chain. By using ScanWorks for PLD programming, the operation can be combined with boundary-scan testing to save time and avoid re-connecting the PCB to a programming station.

The ScanWorks Interconnect Development Station can also load data into devices with the I2C protocol. If the I2C pins are accessible from the boundary-scan pins of an adjacent device, ScanWorks can automatically detect the I2C pins and execute the I2C protocols to load data files into the device. This feature is often used to load board-specific data such as serial numbers and version numbers at test time.

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