ScanWorks^® JTAG Interconnect Development Station Bundle

Diagnosing Defects

Finding defects is only half the battle. You must also be able to isolate the defect to be able to fix it and return the PCB to the manufacturing process. A ScanWorks Interconnect development Station includes several features that help isolate defects, including pin level diagnostic reports and a test results windows that can display test results vector by vector. Additional diagnostic capabilities are available as options. Graphical Fault Highlighting adds the ability to link fault reports to a graphical view of the board layout or schematic to help pinpoint the likely location of a defect. The Debugger and Scan Analyzer interactively control scan operations at the level of a boundary-scan cell or register. These features can also create a waveform view of the test results.

Interconnect Development Station Tests

Scan Path Verification Tests

Scan path verification tests are very important to effective boundary-scan testing. Before any test is applied, you should always verify that the scan path is working correctly. Scan path verification tests are created automatically by the scan path discovery tool or by a single button click in the scan path verify dialog. The test developer is presented with several options so that the test can be configured for a specific application.

To avoid placing devices in a test mode with unknown values on the devices’ outputs, scan path verification tests begin with scans of the data register only. Once the basic data path is confirmed, the instruction register is tested and scans are performed to verify the length of the boundary register. The developer has several options to set alternative values for the device ID codes or user codes.

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