JTAG  
View Leadership Video
New to JTAG/Boundary Scan?

PRODUCTS

BSDL Services:
BSDL Validation Service
ScanWorks®
Boundary-Scan Products:

Interconnect Development Station
Interconnect Repair Station
Test Development Station
Diagnostic & Repair Station
Manufacturing Station
Programming Stations
IEEE 1149.6
Emergency License Tokens
Hardware Overview

IBIST Products:
ScanWorks® Intel® IBIST
Emulation Products:
MicroMaster
ICT Products:
ScanWorks® for Agilent's Medalist ICT
Technology:
Test Automation
System-Level JTAG


FREE RESOURCES & VIDEOS

Free Resources & Videos

 

TRAINING

ASSET ScanWorks Training Classes

 

SUCCESS STORIES

View all our Success Stories

 

 

ScanWorks® JTAG Diagnostic & Repair Station Bundle

Diagnostics

Interconnect Pin-Level Diagnostics

The Diagnostic & Repair Station include diagnostics to the pin level for interconnect tests. The report generated provides the type of fault detected, the most likely source of the fault, information about the net to which the pin is connected, and links to specific nets or pins in the InterComm Design Browser layout view. The report indicates the type of connection for each pin on the net using symbols to indicate input, output, or bi-directional and if the device is a cluster (non-boundary-scan), or unknown.

Memory Access Verification Diagnostics

Tests created with the Memory Access Verification tool can detect defects on data, address and control signals connected between boundary-scan device and non-boundary-scan memory devices. Defects can be diagnosed to the data or address signal, and in some cases to a specific control signal. A diagnostic report that indicates the signal and the specific memory pin involved is generated. Pins are linked to the board layout view provided by the Graphical Fault Highlighting feature, making it easy to locate the suspected pin on the actual board being tested.

A test results dialog is also provided. Like the interconnect debugger, it provides a state table view of the scan operations needed to execute the read/write operations necessary to complete the test. Data is displayed in two modes: A cycle mode that shows only the significant scans for reading and writing to the memory and a vector mode that shows every scan.

Macro Language

The macro programming language provided with a Diagnostic & Repair Station is a powerful, high-level language that provides access to the design at any level; from individual scan cells to entire test registers or subsets of test registers. With specialized functions and procedures you can control or observe a specific pin or create a complete test for a cluster of non-boundary-scan logic. With a macro program you can establish “safe” conditions before entering the boundary-scan test mode or maintain a safe state throughout testing.

Previous : Next                    Page 3 of 4          Back to Page 1

Free Hit Counter Code