ScanWorks® JTAG Diagnostic & Repair Station Bundle

Diagnostics

Scan Path Verify Diagnostics

The boundary-scan design description used in ScanWorks is based on the IEEE 1149.1 standard Boundary-Scan Description Language (BSDL) files provided by the device vendors. The design management software imports these descriptions and creates a description of your design that includes all of the information needed to perform scan operations on the design. Once the design is described, tests to verify the design description against your actual board and tests to verify the scan path is actually working are automatically created.

The full scan path verification generation dialog is provided in the Interconnect Repair Station to give the Repair Technician full access to the diagnostic features. Selecting or deselecting the optional tests enables the technician to quickly isolate scan path defects. Scan path verification tests include options to specify alternate Device IDCODES or USERCODES to support second source devices or different versions of the same device. A test results dialog is included to provide a sate table view of the actual response data during test application.

Interconnect Test Diagnostics

Interconnect test diagnostic tools includes net and pin level diagnostic reports and a built-in test results dialog. The diagnostic report provides all the information available about any net on which an unexpected response is detected, including the most likely type of defect, (open or shorted) and the device and pin information about all other connections to the net.

The test results dialog provides a state table view of the results of applying interconnect tests. Each scan operation is shown for selected pins or nets, enabling you see exactly what conditions lead to miscompares. Miscompares are highlighted and the driving pins are clearly indicated. You can rerun the tests from within the test results dialog and also observe specific pins or set them to specific logic levels.

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