JTAG Guidelines for Board DFT - Part 1: 

BOARD-LEVEL DFT GUIDELINES, PART 1

First, maximize the use of 1149.1-compliant devices. The more JTAG (boundary-scan) register access you have, the more fault-coverage will be obtained: both between BS and BS devices and between BS and non-BS devices. Note also that higher fault coverage can be achieved by using unused boundary-scan (JTAG) pins to control buffer direction and output enable signals of simple devices like Texas Instruments’ 244 and ‘245 buffer devices.

Make sure the BSDL files have been validated. See Chip DFT Guidelines for more on BSDL compliance checking.

Note, some devices, notable IBM LSSD devices use the subordination feature of the 1149.1 Standard. In certain LSSD devices, internal LSSD structures are used to test the internal logic of the device, including the 1149.1 logic (TAP controller, etc). This raises a question: who’s in charge – 1149.1 or the internal test structures? To answer the question, 1149.1 allows an internal test structure, such as LSSD, to be in charge (i.e. 1149.1 is subordinated to LSSD) but when the full 1149.1 feature set is required, certain pins are held at a fixed level. These pins are called compliance pins and they must be directly accessible in order for the part to become compliant to 1149.1.

Compliance-enable pins are also available on certain CPLDs. We will discuss what to do with these pins later.

It is possible to design complex scan-chain configurations at the board level e.g. different TMS lines going to subsets of different devices; direct rather than daisy-chained access to individual TDI and TDO pins; etc. The advice here is: make sure the PC-based board tester can handle such infrastructures and “walk before you run”. If you want to read up on these more-complex structures, take a look at Sasidhar’s paper:

Sasidhar et al., “Testing NASA’s 3D-stack MCM space flight computer”, IEEE Computer Society Design & Test of Computers, July-Sept., 98, pp. 44-55

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