Guidelines for Board Design For Test (DFT) Based on Boundary Scan (JTAG)

This is a two part document that contains a series of DFT Guidelines for boards to be tested primarily through the use of boundary scan, based on the IEEE 1149.1-2001 Standard.

In these documents, we will look at DFT guidelines specific to the design of devices to be tested through the boundary-scan (JTAG) registers of IEEE 1149.1-compliant devices. Since the 1149.1 structures are incorporated inside the compliant devices, many of the guidelines relate to the specification of optional features inside the devices i.e. are device-level DFT guidelines. Accordingly, the first part of the document considers the device-level guidelines.

	In Part 1of the Guidelines for Board DFT, we will look at general DFT guidelines specific to the design of boards to be tested through the JTAG/boundary-scan registers of IEEE 1149.1-compliant devices.
	In Part 2 of the Guidelines for Board DFT, we will look at DFT JTAG guidelines specific to the design of boards containing non-boundary-scan clusters and the special case of RAM and PLD clusters (in-system configuration).