JTAG Guidelines for Board DFT - Part 1:

Guidelines for Board Design For Test (DFT) Based on JTAG or Boundary Scan

Part 1

Prepared by Ben Bennetts, DFT Consultant for ASSET InterTech, Inc.

April 2006

ABSTRACT:

This document is Part 1 of a 2-part document that contains a series of DFT Guidelines for boards to be tested primarily through the use of boundary scan, based on the IEEE 1149.1-2001 Standard.

Any comments, corrections, suggested additions should be sent to the author, Ben Bennetts, at ben@dft.co.uk.

In this document, we will look at general DFT guidelines specific to the design of boards to be tested through the JTAG/boundary-scan registers of IEEE 1149.1-compliant devices.

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