Boundary-Scan Tutorial:

Device Architecture

After nearly five year’s discussion, the JTAG organization finally proposed the device architecture shown in Figure 17.

The Figure shows the following elements:

A set of four dedicated test pins — Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) — and one optional test pin Test Reset (TRST*). These pins are collectively referred to as the Test Access Port (TAP).

A boundary-scan cell on each device primary input and primary output pin, connected internally to form a serial boundary-scan register (Boundary Scan).

A finite-state machine TAP controller with inputs TCK, TMS, and TRST*.

An n-bit (n >= 2) Instruction register, holding the current instruction.

A 1-bit Bypass register (Bypass).

An optional 32-bit Identification register capable of being loaded with a permanent device identification code.

At any time, only one Data register can be connected between TDI and TDO e.g., the Instruction register, Bypass, Boundary-Scan, Identification, or even some appropriate register internal to the device. The selected Data register is identified by the decoded parallel outputs of the Instruction register. Certain instructions are mandatory, such as Extest (boundary-scan register selected), whereas others are optional, such as the Idcode instruction (Identification register selected).

Mandatory Instructions and Reset Modes

Before we look closer at each part of this architecture there are two general points to note about Figure 18:

Point 1. Since 1149.1-2001, the latest version of the Standard, there are only four mandatory instructions: Extest, Bypass, Sample and Preload.

Point 2. The asynchronous Reset signal, TRST*, is optional. If present, the signal is active low. If not present, there is always a synchronous reset available within the TAP controller. If TMS is held at logic 1, a maximum of five consecutive TCKs is guaranteed to return the TAP controller to the reset state of Test_Logic Reset. This will be referred to as the TMS = 1, 5 x TCK synchronous reset.

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