Boundary-Scan Tutorial:

Basic Boundary-Scan Cell (BC_1)

Figure 13 shows a basic universal boundary-scan cell, known as a BC_1 . The cell has four modes of operation: normal, update, capture, and serial shift. The memory elements are two D-type flip-flops with front-end and back-end multiplexing of data. (As with all circuits in this tutorial, it is important to note that the circuit shown in Figure 13 is only an example of how the requirement defined in the Standard could be realized. The IEEE 1149.1 Standard does not mandate the design of the circuit, only its functional specification.)

During normal mode, Data_In is passed straight through to Data_Out .

During update mode, the content of the Update Hold cell is passed through to Data_Out .

During capture mode, the Data_In signal is routed to the input Capture Scan cell and the value is captured by the next ClockDR . ClockDR is a derivative of TCK.

During shift mode, the Scan_Out of one Capture Scan cell is passed to the Scan_In of the next Capture Scan cell via a hard-wired path.

Note that both capture and shift operations do not interfere with the normal passing of data from the parallel-in terminal to the parallel-out terminal. This allows on the fly capture of operational values and the shifting out of these values for inspection without interference. This application of the boundary-scan register has tremendous potential for real-time monitoring of the operational status of a system — a sort of electronic camera taking snapshots — and is one reason why TCK is kept separate from any system clocks.

The use of boundary-scan cells to test the presence, orientation, and bonding of devices was the original motivation for inclusion in a device. The use of scan cells as a means of applying tests to individual devices is not the major application of boundary-scan architecture. Consider the reason for boundary-scan architecture in the first place. The prime function of the bed-of-nails in-circuit tester was to test for manufacturing defects, such as missing devices, damaged devices, open and short circuits, misaligned devices, and wrong devices. See Figure 14.

In-circuit testers were not intended to prove the overall functionality of the on-board devices. It was assumed that devices had already been tested for functionality when they existed only as devices (i.e., prior to assembly on the board). Unfortunately, in-circuit test techniques had to make use of device functionality in order to test the interconnect structure — hence the rather large libraries of merchant device functions and the problems caused by increasing use of ASICs.

Given that boundary-scan registers were seen as an alternative way of testing for the presence of manufacturing defects, we should question what these defects are, what causes them, and where they occur.

An examination of the root cause for board manufacturing defects shows them to be caused by any one of three reasons: electrical stress (e.g., electrostatic discharge causing damage to input or output amplifiers), mechanical stress (e.g., bent legs caused by clumsy handling when mounting devices on the board), or thermal stress (e.g., hot spots caused by the solder operation). A defect, if it occurs, is likely present either in the periphery of the device (leg, bond wire, driver amplifier), in the solder, or in the interconnect between devices. It is very unusual to find damage to the internal logic without some associated damage to the periphery of the device.

In this respect, the boundary-scan cells are precisely where we want them — at the beginning and ends of the region most likely to be damaged during board assembly i.e. the region between the output driver scan cell and the input sensor scan cell. This region is more-commonly referred to as the interconnect region.

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