PRESS ROOM - AUTHORED ARTICLES

Making moves from board to system test

By Reg Waller, ASSET InterTech, Inc.
Electronics Manufacture and Test, (June 2005) p. 11

Boundary scan (IEEE 1149.1/JTAG) is most often thought of as a board-level test method, but new hardware and software techniques make system-level test with boundary scan not only feasible, but quite effective. Reg Waller explains.

System-level tests with boundary scan can save a significant amount of time and effort troubleshooting systems. Many different types of faults can arise when electronic systems are assembled. JTAG testing techniques are well suited to finding and diagnosing many of these problems.

For the purposes of this article, an electronic system implies two or more circuit boards connected together. This could be something as simple as a motherboard/daughterboard assembly or an extremely complex backplane-based computer with hundreds of boards.

Deploying System-Level JTAG Tests
Four primary methods are available for implementing boundary-scan tests at the system-level. Three of these methods require connecting an external boundary-scan test tool to the system while the fourth involves embedding boundary-scan test capabilities into the system.

Single-path system test
The first external test method concentrates all of the boundary-scan paths on all of the boards in the system into a single scan path with one point of access for the boundary-scan test system (Figure 1). This method requires that the configuration of the system is identical in every assembled product.

Multiple Paths/Multiple Connectors
A second external method would involve linking the multiple scan paths present in the system to multiple external connectors where the boundary scan tool could access all scan paths.

Test Gateways
A third alternative would be to design into the system a method for controlling access to scan paths on individual boards from one external JTAG test access port (TAP) (Figure 2). This is most commonly accomplished with multidrop gateway devices that control the board on which the device is located for the purposes of testing the system.

Embedded System Test
A fourth method, which does not require the direct connection of an external boundary-scan test system, would be to embed JTAG-compatible built-in-self-test (BIST) features into the system. This is usually the most efficient method because it can provide fast test times and high fault coverage if it is designed properly. Embedded BIST-based boundary-scan tests must be designed into a system early in the design cycle, because they can not be easily retrofitted into the system. Embedded boundary-scan BIST can be controlled by an on-board test manager and initiated via most of the more prevalent functional user interfaces. Alternatively, embedded system tests can be initiated by a test interface via the boundary-scan TAP.

Merging Board Tests into System Tests
The growing deployment of board-level boundary-scan testing in recent years has made it considerably easier to implement system-level boundary-scan operations because the test-development work for individual board test can be leveraged against system-level objectives. Presumably, the board-level boundary-scan infrastructure is already in place and this can be utilized by system-level boundary-scan tests. As a result, the payback on system-level testing can be quite rapid since the amount of development time needed to implement system tests as an add-on to board-level boundary-scan operations is limited.

Still, there are issues that the test engineer must consider as board-level boundary-scan tests migrate to system-level test suites. Board tests can not be simply added together to create a system test suite since this might connect all of the input/output (I/O) on a given board with the rest of the I/O in the system. The boundary-scan tests should not generate contention by driving signals that may also be driven by other boards in the system. One solution would be to isolate the boards in the system while the boundary-scan tests are being applied to each particular board. This can be done within the boundary-scan system test suite by disabling backplane signals while boundary-scan tests are being applied to individual boards. This assumes that the boundary-scan test system, if the system test suite is applied from an external boundary scan test system, has access to all of the boards in the system.

Some boundary-scan test systems support system-level tests better than others. For example, the boundary-scan system should have hardware to connect to multiple scan paths and software to manage the access to those paths. Some sophisticated boundary-scan systems are adaptable enough to access each scan path individually or multiple scan paths can be concentrated together into groups so that the interconnects among boards can be tested.

The value that boundary scan brings to board test is well established. Capabilities like precise diagnostics, fault isolation and identification down to the level of individual pins on devices and others are as valuable at the system level as they are at the level of individual boards. As a result, boundary scan is rapidly becoming a critical technology for testing electronic systems at every level.

The author is European Sales Director for ASSET InterTech.

ASSET InterTech Tel: 01438 750050

Web: www.asset-intertech.com