ASSET InterTech's Boundary-Scan Test, Processor-Controlled Test and Intel® IBIST form a unique set of tools for access to, and control of embedded instrumentation.
July 14, 2010 - ASSET® InterTech (www.asset-intertech.com), the leading supplier of open tools for embedded instrumentation, will integrate test adapter intellectual property (IP) from IPextreme into its ScanWorks® platform for embedded instruments to enable chip and circuit board tests under the new IEEE 1149.7 reduced-pin boundary scan standard. Read more »
ScanWorks validation and testing tools for Intel®’s future. Circuitnet, March 2010
ASSET’s Al Crouch discusses innovative test strategies for 3D stacked die chips. 3Dincites.com, December 2009
Best in Test Finalists 2010: DFT, boundary scan, and emulation, Test & Measurement World, December 2009
ASSET's ScanWorks Supports PLX Technology's PCI Express Switch Family's visionPAK Diagnostic Toolset, PCBCafe, November 2009
Strategic Relationship with SiliconAid Extends ASSET's ScanWorks Platform Into Chip Test and Verification, Evaluation Engineering, November 2009
ASSET InterTech's Dehne - Seeking Growth in Embedded Instrumentation, Test & Measurement World, July 2009
"Driving 3D Chip and Circuit Board Test into High Gear" by Al Crouch, CTO Core Instruments, Future-Fab International, April 2010
"3D-Chips auf dem Vormarsch: Herausforderungen bei Testverfahren" by Glenn Woppman, President & CEO, Embedded Design Germany, April 2010
"TAP und IJTAG: Synergie zweier zukunftsträchtiger Standards" by Glenn Woppman, EPP Europe, March 2010
"Embedded Instrumentation Has Intel® Xeon® Processor 5500 Series Designs Covered” by Tim Caffee, Embedded Intel Solutions Winter 2010
IEEE 1149.7 and P1689 - dispelling the misconceptions
ScanWorks® delivers the test coverage that ICT can't
“Embedded Diagnostics for Highly Available Systems”
By Larry Osborn, Technical Product Manager, Processor-Controlled
Test and Alan Sguigna, Vice President, Sales and Marketing
April 2010
“Doing
More with Less - An IEEE 1149.7 Embedded Tutorial: Standard
for Reduced-pin and Enhanced-functionality Test Access Port and
Boundary-Scan Architecture”
By Adam Ley, chief technologist – boundary scan test
ITC, November 2009
“Defect
Coverage for Non-Intrusive Board Tests”
By Adam Ley, chief technologist – boundary scan test
November 2009
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September 13-16
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San Francisco, CA
September 13-15
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Test Conference)
Austin, TX
October 31 - November 5
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