ASSET InterTech's Boundary-Scan Test, Processor-Controlled Test and I/O Instrumentation for Intel® IBIST are unique tools for access, automation and analysis of embedded instrumentation.
ScanWorks® interconnect pin-level diagnostics provides an easy-to-use and effective means of identifying manufacturing defect faults discovered during interconnect testing. Building on the standard diagnostic capabilities of ScanWorks, the pin-level diagnostic software provides detailed fault diagnosis down to the pin and device level. The interconnect pin-level diagnostics detects and reports all common error types, such as different stuck-at conditions and bridging faults. In addition, the report provides an indication of additional fault types, such as opens and bad bi-directional cells.
The first step in producing good diagnostics is creating correct test vectors. Vectors must be generated correctly to properly identify failures and isolate faults. Generation of the interconnect vectors is provided using the ScanWorks Development Licenses’ automatic interconnect test vector generation capability.
After the test vectors have been created, use any of the ScanWorks Licenses to apply the vectors to your unit being tested. During application, ScanWorks requires the actual response vectors from the unit being tested. The response vectors can be analyzed immediately or saved for diagnosis at an offline Repair License.
Most defects found in board manufacturing processes are open and short in the interconnect structures between devices. These defects can be detected and diagnosed using interconnect pin-level diagnostics. An interconnect structure starts with one or more driver scan cells in one device and terminates with one or more receiver scan cells in other devices. Between the driver and receiver cells lie the internal bond wires, driver and receiver amplifiers, pins, solder connections, and external wiring connections. The detectable faults and diagnostic accuracy vary according to the structure.
This is the simplest form of interconnect. Typical defects are net stuck-open or net shorted to power or ground anywhere between the drivers scan cell and the receiver scan cell. The stuck-open is detected at the receiver as a stuck-at-1 or stuck-at-0 fault, depending on technology. The short is detected as a stuck-at-1 (short-to-power) or stuck-at-0 (short-to-ground). Diagnosis of the short will be to the net, but not to the driver or receiver end of the net.
If an open or short exists at the driver end of the interconnect net, these faults are detected at all receivers and diagnosed as per the single driver/single receiver case. An open at one of the receivers is detected and located at that receiver as a stuck-at fault. A short to power or ground is detected by all receivers as either stuck-at-0 or stuck-at-1. Diagnosis of the short is to the net-to-net connection.
An open at one of the drivers causes that driver to be unable to influence the value on the net. This defect is detected at the receiver and diagnosed as a stuck-fault associated with the driver. A power or ground short on one of the drivers is detected at the receiver and diagnosed as a net stuck-at fault.
An open at any driver is detected at all receivers with diagnosis similar to the multiple drivers/single receiver fault. An open at one of the receivers is diagnosed as a stuck fault at the receiver. A short to power or ground is detected at all receivers and diagnosed as a net stuck-at fault.
Defects on the driver cell of a three-state driver are detected and diagnosed the same as above. Open-circuit defects on the tristate control cell is detected as driver output floating; whereas shorts on the tristate control cell are diagnosed as driver output floating or driver output stuck-at depending on whether the short is to the cell-enable or cell-highZ value.
Opens and shorts on bidirectional drivers/receivers are treated as supersets of the tristate and single driver/single receiver faults. Opens are located to the bidirectional cell causing the problem, either as a driver or a receiver. Shorts are diagnosed either to the net (bidirectional cell, stuck-on fault) or to the driver cell (bidirectional cell, stuck-Z fault). Leaky bidirectional (and tristate) drivers are diagnosed as long as the effect produces a hard stuck-at fault.
Two separate scan-interconnect structures can be shorted together (a bridging fault, usually caused by solder-to-solder flow). If the short behaves logically, diagnosis is to the two nets, covering the wired-AND, wired-OR, and strong driver behavior of the short.
A cluster fault is a short circuit between two nets, one of which is a scan net (scan driver to scan receiver) and the other is a non-scan net (non-scan driver to non-scan receiver). Under some conditions, scan testing can detect the short, but diagnosis may be difficult.
When authorized, interconnect pin-level diagnostics replace the net-level diagnostics that are provided with the interconnect test generation tool. The diagnostic report is generated as the tests are applied and is immediately available. The report is available in text or HTML format. The report indicates the pin to which the fault has been diagnosed, along with addition information about the net to which it is connected. Each connection is identified as an input, output, bidirectional, or cluster (non-boundary scan) pin, if known. Each pin listed is linked to the design browser, which can be viewed by clicking on the pin name. The physical pin location is indicated on the design layout view with cross hairs.
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