Two new whitepapers address board test coverage and standards for 3D chip test

ASSET’s chief technologists, Adam Ley and Al Crouch, have been busy compiling informative whitepapers on two distinct topics.

Adam’s whitepaper is titled “Defect Coverage for Non-Intrusive Board Tests.” It describes the evolution of test technologies and methodologies from intrusive external instrumentation like in-circuit test (ICT), flying probe, manufacturing defect analyzers and others to non-intrusive embedded instrumentation technologies, such as boundary scan, processor-controlled test, built-in test and others.

The paper goes on to describe several methodologies for quantifying test coverage, such as the PCOLA/SOQ/FAM method that has been proposed by iNEMI (International Electronics Manufacturing Initiative). The paper concludes with a case study on how a non-intrusive board test strategy can deliver comprehensive test coverage on an Intel® Xeon® Processor 5500 Series platform. To read Adam’s whitepaper, click here.

The second new whitepaper, which was written by Al Crouch, chief technologist, core instrumentation, is titled “Synergy of Two Emerging Standards Will Drive 3D Chip and Circuit Board Test into High Gear.” Al’s whitepaper discusses how the challenge of 3D chip validation and test is being met with the emergence of the IEEE 1149.7 Standard for Reduced-Pin and Enhanced Functionality Test Access Port and Boundary-Scan Architecture and the IEEE P1687 Internal JTAG (IJTAG) standard for accessing on-chip embedded instrumentation. IEEE 1149.7 was recently ratified and will be published soon. Approval of the IEEE P1687 standard is expected during the third or fourth quarter of 2010.

To read Al’s whitepaper, click here.