Embedded instrumentation overcomes variations in manufacturing
By Eric Johnson
Product Manager, I/O Instrumentation
Achieving robust high-speed input/output (HSIO) channels on a circuit board design while maintaining a reasonable product cost is a delicate balancing act. Designers walk this tightrope every day and use all of the tools at their disposal to simulate and validate that the links on a particular board design will meet spec and have sufficient margin before going into high-volume production.
As covered in part one of this article (Click here for part one), nearly everything about the printed wiring board (PWB) manufacturing process can affect the quality of HSIO links. In the multi-gigabit per second (Gb/s) range, the tolerances on trace width, layer thickness, dielectric constant, trace roughness and others will all affect the integrity of the signals the receiver sees. This is particularly critical now as high-speed serial buses climb to higher and higher data rates. For example, PCI Express Gen 3 can achieve rates of 8 Gb/s while SATA III is already at 6 Gb/s, USB 3.0 speeds along at 4.8 Gb/s and HDMI 1.3 is capable of 10.2 Gb/s.
Beyond simple tolerances, changes to manufacturing processes or vendors of various parts and materials can take the links on a previously good design out of spec. According to Arden Bjerkeli in the first part of this article, variances affecting signal integrity can stem from many different causes. “In addition to PWB process variances, random variances (defects) are also expected to impact signal integrity. These include incompletely plated vias, annular ring breakout, flaws introduced during the imaging process (i.e. pinholes, nicks, cuts), plating thickness variations and delamination.” 1
Work from the Mayo Clinic2 presented at the recent DesignCon 2010 showed that there are significant variations in S-parameter measurements across a single board and across multiple boards within the same lot. These measurements translate into differences in insertion loss, impedance, and eye height and width at the receivers.
There is also empirical evidence that for a given board design the amount of margin, the training values and margin lane failures all follow the device supporting the bus.3 This is as might be expected since parts are typically “binned” by suppliers based upon performance attributes. Finally, manufacturing process variations from assembly, such as solder voids, micro-cracks, “head-in-pillow” defects, and others affect transmission line integrity at multi-gigabit rates.4
These problems are very real for the industry today with I/O speeds in the 5 Gb/s range and the difficulties will only continue to grow as data rates continue to climb. A one-time validation at the conclusion of the design process will no longer be sufficient to provide a solid product at a competitive cost. Some of our validation steps need to move from design engineering into production and field test in order to ensure sufficient performance from design to end-of-life.
Of course, it’s not reasonable to bring test equipment like oscilloscopes and vector network analyzers (VNAs) into the main production flow and these certainly can’t be deployed for field repair. Hardware-based testers are high-cost items, require expert users and would take far too long to test every high-speed net on a board with direct probing in production. And, probing signals in the Gb/s range is an art form of itself, often requiring a dedicated probing station and simulation to isolate the effects that fixtures and probes have on measurements.
The emergence of embedded instruments in chips provides us with a new approach to solve these problems.
The Emergence of Embedded Instrumentation
Many of today’s chips already have instruments embedded in them. These embedded instruments can be accessed with a software solution like ScanWorks® to allow on-board testing without the need for external hardware testers. With ScanWorks driving the embedded instruments inside the chips, the only external hardware required is a small, low-cost interface pod. Rather than relying on hardware-based measurements, simulation and user interpretation of specifications and results, embedded instruments provide true, uncorrupted results from the receiver itself. Embedded instrumentation tests use the same receiver that is employed in normal functional modes. There is no interpretation of results by the tester since the actual functional receiver is the test point.
An example of this use of embedded instrumentation is the Intel® Interconnect Built-In Self Test. IBIST embedded instrumentation capabilities are included in some Intel processors and chipsets such as the Intel® Xeon® Processor 5500 Series. Not only can IBIST tests detect structural faults, but these tests can also provide information about the performance and quality of the links.
The overall test strategy for Intel® Xeon® Processor 5500 Series-based designs focuses particularly on high-speed buses such as QuickPath Interconnect (QPI) and PCI Express (PCIe) interconnects. With IBIST, functional tests can be performed on these buses using pseudo-random bit sequence (PRBS) patterns as a foundation for pattern generation and checking (PG&C), bit error rate testing (BERT), and margining.
Basic PG&C tests can detect many structural faults, but high-speed serial nets like QPI and PCIe are designed to be immune to common mode noise such as that induced by some structural faults. In these cases the links will “appear” to operate normally to many types of test technologies and can even work functionally. The more advanced capabilities of IBIST’s BERT and margining embedded instruments are required to detect performance degradation due to structural faults or variances in device, materials or process changes.
Rather than attempting to measure low-level parameters such as insertion loss and impedance variations in order to make calculations to determine the performance of the link, IBIST instruments can be used to determine bit-error-rate and margin data such as eye height and width from the receiver inside the chip itself. This provides data directly from the functional receiver without requiring modeling and simulation to de-embed probe and fixture effects. With this direct measurement, there is no user interpretation of passing vs. failing bits.
Click here to enlarge.
Caption: The composite view of the cross margin test shows where all lanes are passing in green, some lanes are failing in yellow, and all lanes have failed in red. Blue indicates some lanes were still passing at the maximum allowed range.
Overcoming Variances
As described in the first part of this two-part article, variances encountered over the course of volume manufacturing can cause circuit boards to drift outside of their operating range. Also it is known that systems deployed in the field can suffer from degraded performance or fail over time due to environmental factors or the effects of silicon aging6. A proactive approach to signal integrity in the factory is the new standard for the next generation of high-speed buses and this will be enabled by embedded instrumentation.
Footnotes
1 “Variances in PCB manufacturing processes can betray confidence in SerDes designs”, A. Bjerkeli, ASSET InterTech, Connect September 2009.
2 “PWB Manufacturing Variability Effects on High Speed SerDes Links: Statistical Insights from Thousands of 4-Port S-Parameter Measurements”, Bart O. McCoy, Mayo Clinic, DesignCon 2010.
3 “Platform Validation Using Intel® Interconnect Built-In Self Test (Intel® IBIST), S. Akimoff, ASSET InterTech, DesignCon 2009.
4 “Structural testing of high-speed serial buses – A Case Study Analysis”, E. Johnson, ASSET InterTech, International Test Conference 2006.
References
“Intel® IBIST, the Full Vision Realized”, J. Nejedlo, R. Khanna, Intel Corporation, International Test Conference 2009. |
