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OBSERVATIONS

Connecting the dots:
Global recovery, Moore’s law, chip packaging and test

Glenn Woppman
President and CEO
ASSET InterTech

Experts are predicting that chip innovations – specifically, new 3D packaging technologies – will boom as the global economy recovers. Others say 3D chip technology is the most feasible means for the industry to continue following Moore’s law. The fly in the ointment could be test. How are 3D chips going to be tested at the package level? And how are they going to be tested once they’ve been placed on circuit boards? Standards and tools are being developed that address these questions and others. And, once again, ASSET is in a leadership position.

TEST DATA OUT

New IJTAG standard will generate millions for chip and system manufacturers

By Al Crouch
Chief Technologist—Core Instrumentation

As the new IEEE P1687 Internal JTAG (IJTAG) standard inches closer to ratification, the big picture of the standard’s economic benefits is emerging. Quite simply, P1687 will maximize the return-on-investment (ROI) that chip suppliers are making in embedded instrumentation and give circuit board and system manufacturers the ability to reap their own significant economic benefits.

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Article details the emerging standards for 3D chip test

A recent article by Al Crouch, ASSET’s chief technologist – core instruments, on SOC Central, a web site and e-newsletter for engineers involved in chip, ASIC and SOC design as well as EDA tools, details the advancements that are being made in standards-based 3D chip testing and why new validation and test methodologies will be so critical to improving yield rates. Click on the link below for a summary of Al’s article and a link to the complete text.

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With approval nearing, ASSET’s 1149.7 tutorial is timely

The IEEE P1149.7 Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture recently entered its recirculation ballot. In all likelihood, then, by the end of the year, 1149.7 should achieve final approval. So, the timing of an 1149.7 tutorial at the upcoming International Test Conference (ITC) couldn’t be better. Adam Ley, ASSET’s chief technologist-boundary scan, will present the 1149.7 tutorial as part of the Embedded Tutorial track at ITC.

INSIDE ASSET

New whitepaper explores NBT test coverage

Much is being made in the industry concerning the application of embedded instrumentation in board test applications. In fact, non-intrusive board test (NBT) technologies are rapidly emerging as alternatives to the older intrusive test technologies like in-circuit test (ICT). Adam Ley, ASSET’s chief technologist—boundary scan, has decided to take a close look at the test coverage provided by NBT because, in the final analysis, cost-effective test coverage is what the test industry is all about. Adam’s new whitepaper, “Defect Coverage for Non-intrusive Board Tests,” asserts that NBT recovers the test coverage that has been lost by the older intrusive test technologies in recent years.

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User Group morphs into ScanWorks Open Forum at ITC
Chip-level case studies slated on the IJTAG embedded instrumentation standard, processor-controlled test and others

Since this year’s ASSET User Group will convene at the upcoming International Test Conference, the meeting will be open to interested non-users who may be attending the conference in the Austin Convention Center. As a result, the name of this meeting has been changed to the ScanWorks Open Forum. Several users will share their experiences with ScanWorks, including a presentation from EMC on processor-controlled test and another from Flextronics on its use of the emerging IEEE P1687 Internal JTAG Standard.

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ASSET will have major presence at upcoming ITC

ASSET’s presence at the upcoming International Test Conference (ITC) in Austin, Texas, can’t be measured by the linear dimensions of its booth (which, by the way, will be No. 117). Of course, the ASSET booth is not to be missed but in addition to the buzz created by the exciting demos in the booth, ASSET personnel will be involved in presenting tutorials, technical papers, posters, corporate presentations, panel discussions and workshops. And then there’s the ScanWorks Open Forum meeting too. ITC is shaping up as a busy week indeed.

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ASSET’s Productronica stand highlights ‘no-nails’ testing

ASSET’s live demonstrations in its stand (Hall A1, Stand 470) at Productronica in Munich, Germany, Nov. 10 – 13, will highlight the diminishing test coverage from intrusive, probe-based test technologies and demonstrate the increasing test coverage offered by non-intrusive board test (NBT). The demonstrations will concentrate on ASSET’s ScanWorks platform for embedded instrumentation and show how software-driven test technologies like boundary scan test, processor-controlled test and Intel®’s Interconnect Built-In Self Test (IBIST) deliver high test coverage for designs based on Intel® Atom™ processors, the Intel® Xeon® Processor 5500 Series and a wide range of processors, including AMD®, ARM®, PowerPC™ and others.

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A test fable…Part 2

Norm figures a way out of the NTF conundrum

When we last looked in on Norman Thomas Follett, or NTF as he is affectionately known to his colleagues in field service (the really cruel colleagues called him ‘No Trouble Found’), he was puzzling over an intermittent and recurring problem with his company’s routers in the field. He’s still puzzling, unfortunately. Circuit boards are failing under mysterious circumstances and testing them in the lab is no help. They perform like champs in the lab. That was part of the puzzle, but how was Norm to know when the tools he had couldn’t come close to telling him that the problem stemmed from memory traps and a failed BIOS flash load?

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New interposer opens test access to the Intel® Xeon® processor 5500 series and Core™ i7 processors

The new LGA1366 interposer gives test access to the debug port on several of Intel®’s processors that are based on the new Nehalem microarchitecture, such as the Xeon® processor 5500 series and the Core™ i7 processors. Typically, production circuit boards will not include circuitry to the processor’s debug port or the connector is not included on the board. Now, with the ScanWorks® platform and the LGA1366 interposer, the debug port can be accessed for a variety of tests, including processor-controlled test (PCT).

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ASSET in the news:

Two technical articles focus on embedded instrumentation and 3D chip test

Al Crouch, ASSET’s chief technologist-core instrumentation, has authored two articles. One will appear next month in a prominent European electronics magazine, Elektronik Informationen, which will be distributed at the Productronica conference in Munich, Germany. The second article was recently featured on a well regarded technical web site in the U.S., SOC Central. Al’s article in Elektronik Informationen discusses emerging tools for embedded instrumentation while the article on SOC Central explained two standards that will be applied in the testing of 3D chips.

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Social networking is the craze these days,
but are you crazy about it ?

With the world abuzz about social networking, we’re wondering if the users of the ScanWorks platform for embedded instrumentation would find it helpful if our Technical Support Department was active on one or more of the popular social networking sites like Twitter, LinkedIn, Facebook, Plaxo, MySpace or others. For us to know, you’ll have to share your thoughts with us and that means a painless five-question survey. We promise; it can be completed in less than five minutes.

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PCB Variances: Part 2 - article postponed

Because of the volume of articles in this issue of Connect, Part 2 of an article from the previous issue, “Variances in PCB manufacturing processes can betray confidence in SerDes designs,” has been postponed until the first quarter 2010 issue. Watch for it then.

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