ASSET will have major presence at upcoming ITC

There will certainly be a lot going on for ASSET at ITC 2009 in Austin. One of the key demonstrations in the ASSET booth (No. 117) will be a user case study involving the deployment of three embedded instrumentation technologies in a board test application. Specifically, the circuit board tested in the demonstration is the Intel® Green City customer reference design (CRD) featuring the new Xeon® Processor 5500 Series (Nehalem).

A video demonstration examines the comprehensive test coverage delivered by three of the ScanWorks platform’s embedded instrumentation technologies -- boundary-scan test, processor-controlled test (PCT) and Intel’s Interconnect Built-In Self Test (IBIST). These test technologies can apply embedded instrumentation in non-intrusive board test applications. The demonstration will be running continuously in the ASSET booth at ITC.

The first of the sessions where ASSET has a presence will be a session of technical papers on Tuesday, Nov. 3, at 4 p.m. This session, which is called “Understanding Frequency Behavior on a Device,” will be chaired by ASSET’s Al Crouch, chief technologist - core instruments. Technical papers by representatives of Intel, Sun Microsystems and the University of California, Santa Barbara, will be presented. 

Later on Tuesday, two posters will be presented and explained by ASSET experts. The poster session begins at 5:30 and concludes by 7 p.m. Adam Ley, ASSET’s chief technologist - boundary scan, will present a poster entitled “Defect Coverage of Nonintrusive Board Tests (NBT): What does it mean when a nonintrusive board test passes?” In addition, Al Crouch will join representatives of Avago and Advanced Micro Devices to present a poster called “IEEE P1687 IJTAG: A presentation of current technology.”

Wednesday between 1:30 and 3:30 p.m. will be the time for embedded tutorials from ASSET. Adam Ley and Al Crouch will conduct separate tutorials concerning new boundary-scan-based standards. Adam’s tutorial is called “Doing More with Less—An IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture.” Al will be joined by a representative of AMD for a tutorial entitled “IEEE P1687 (IJTAG) Hardware and Software Architectures.”

On Thursday, Al Crouch will take part in a panel and a workshop. The panel on “How (Un)Affordable Is the True Cost of Test?” will take place at 2 p.m. Joining Al on the panel will be experts from Texas Instruments Incorporated, Sun Microsystems and Cisco Systems. Later that day or possibly on Friday (check the schedule at the show), Al will chair a workshop on “Defect- and Data-driven Testing.” Several papers are expected to be presented on this topic.