Two technical articles focus on embedded instrumentation and 3D chip test

Two articles by Al Crouch, chief technologist-core instrumentation, address different aspects of embedded instrumentation. Al’s article in the November issue of Elektronik Informationen will describe what embedded instrumentation is, why it is becoming increasingly critical in today’s electronics industry and how the tools for embedded instrumentation are emerging. This particular issue of Elektronik Informationen will be distributed at the Productronica trade show in Munich, Germany, Nov. 10-13. ASSET will have a presence at the show in Hall A1, Stand 470.

In addition, a second article by Al appeared in the October issue of the SOC Central e-newsletter, which was distributed Oct. 5. Click here for a summary of this article and a link to the full article on the SOC Central web site. This article explains how two emerging standards, the IEEE P1149.7 Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture and the IEEE P1687 Internal JTAG (IJTAG) standard, will provide the basis for effective test methodologies for 3D chips.

Click here for an article on the IEEE 1149.7 standard in this issue of Connect by Adam Ley, ASSET’s chief technologist-boundary scan, and the major contributor of the test content in this new standard.