With approval nearing, ASSET’s 1149.7 tutorial is timely

Adam Ley
Chief technologist—boundary scan

At the upcoming International Test Conference (ITC) in Austin, Texas, Nov. 1-6 (http://www.itctestweek.org), Adam Ley, ASSET’s chief technologist for boundary scan, will present a tutorial on the soon-to-be-ratified IEEE Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. Approval of 1149.7 is expected by the end of the year, so the timing of the tutorial couldn’t be better.

Adam’s 1149.7 tutorial will be part of ITC’s Embedded Tutorial track and take place on Wednesday, Nov. 4, at 1:30 p.m.

The one-hour tutorial will take an in-depth look at 1149.7, starting with an explanation of the evolution of 1149.7’s foundational standard, the IEEE 1149.1 Boundary-Scan Standard. The 1149.7 working group went to great lengths to make the new standard fully backward compatible with the original 1149.1 boundary-scan standard. The group felt that this would speed adoption of 1149.7 since a compatible infrastructure of 1149.1 boundary scan would already be prevalent in the industry. Because of the compatibility of the two standards, chips that have 1149.7 Test Access Ports (TAP) are fully functional on the same circuit board or module with chips that feature 1149.1 TAPs. This interoperability allows boundary-scan tests across .7 and .1 chips on the same board.

As the name of the new standard implies, the intent of the working group was to develop a TAP and associated architecture that would offer a reduced pin-count and enhanced functionality. Instead of the four-wire 1149.1 interface with an optional fifth wire, 1149.7’s TAP requires only two signals, although a given 1149.7 implementation may include all 4 (or 5) signals.

In addition to the legacy infrastructure of 1149.1, two other key considerations occupied the 1149.7 working group. These were system architecture and applications debug.

System architecture refers to the inclusion in the standard of several innovations. For instance, multiple on-chip embedded TAP controllers are possible under the 1149.7 standard. This and other features of the 1149.7 standard, such as its reduced pin count and a new glue-less star topology, give engineers significantly enhanced capabilities for testing 3D chips individually and after they have been soldered onto a circuit board.

Because 3D chips are made up of multiple die, each die must have its own TAP controller and associated architecture. The two-wire interface of 1149.7 and its glue-less star topology are critical for testing 3D chips. Interfaces wider than two wires embedded in multi-die chips would prove unwieldy and costly in compact 3D chip packages, such as system-in-package (SiP) and package-on-package (PoP). The glue-less star topology (see below) can also be utilized effectively in 3D chips of multiple die.

IEEE 1149.7’s two-wire star topology

Other interesting aspects of the 1149.7 standard include packetization of both scan and background data across the infrastructure. As a result, the standard supports six capabilities classes. The capability classes are configured in the 1149.7 TAP controller to fulfill the needs of the implementation.

1149.7 includes an extension of 1149.1’s Boundary-Scan Description Language (BSDL), referred to as BSDL.7. Since a test module might contain other test modules as sub-components, 1149.7 specifies a Hierarchical Scan Description Language (HSDL.7), which is also based on BSDL.1.

Adam’s tutorial at ITC will certainly contain a deeper level of detail on the new 1149.7 standard. Future issues of Connect will also feature information on the 1149.7 capabilities of the ScanWorks platform for embedded instrumentation.

For a previous Connect article about 1149.7 by Adam Ley, click here.