Variances in PCB manufacturing processes can betray confidence in SerDes designs

By Arden Bjerkeli
Director of Customer Application Support
ASSET InterTech

Confidence in a SerDes (serializer / deserializer) design on a printed circuit board (PCB) is often based on running bit error rate (BER) and other validation tests on one of the first batches of manufactured boards. Typically, the boards are cycled through a range of temperatures and supply voltages and confidence levels are built up, assuring the design team that BER will remain below a certain level even with variations in the manufacturing process of the chips on the board and the board itself.

Unfortunately, these confidence levels are not always well founded since they are sometimes based on a single batch of manufactured PCBs from only one supplier. The boards in this batch may or may not represent the mean manufactured board over the foreseeable future. In fact, since it was the first batch, the supplier might have paid unusually close attention to higher quality, which would have made the SerDes performance margin appear wider than what will be possible in volume production.

There are a number of variations that can be expected during volume production of a PCB and many of these will affect the eye diagram of a SerDes transmission line. This raises the question whether performing margin and BER testing only once during design validation is adequate?

This article provides some examples of manufacturing variations that can have far reaching effects on SerDes performance over the entire product life cycle. The second part of this article in the next issue of Connect will provide solutions based on embedded instrumentation technology.

Design Intent vs. Manufacturing Reality

Even following all of the design rules and recommended practices in selecting the parameters for transmission line layout, there still will be variances and flaws during the production of a PCB that will modify the performance of transmission circuits. Any one variance may not cause the PCB to fall outside the acceptable tolerance range, but the cumulative effects of several variations may yield unacceptable results.

By design, error detection and correction techniques will allow the design to overcome some manufacturing process variations. But, on the down side, these same techniques can make it difficult to catch marginal faults during a quick factory functional test. And traditional structural tests are not designed to catch at-speed marginal faults.

Margin and BER tests can expose these variances, but they take more time than structural tests and typical factory functional tests. Therefore, it may only be practical to perform these tests on production printed circuit assemblies (PCA) when performance is highly critical to the customer. As an alternative to performing these tests on every PCA, it may be wise to run margin and BER tests on samples of production boards throughout the life cycle of the product, especially when there are vendor changes, re-spins or known process changes. But while some PCB process variants can be caught by sampling at the batch level, other flaws and process variants might only affect a single board's performance.

During design validation, the performance margins on a transmission line are typically measured by creating eye diagrams. However, it is not practical to vary PCB tolerances to see how the margins hold up. Some simulators attempt to model the effect of PCB tolerances to help visualize their effects on margins. While simulation improves confidence in a design, it is not a substitute for actual testing. One solution is to repeat some validation steps throughout the life of the product. Fortunately, the emergence of embedded instruments is making this approach increasingly practical.

Process Variants in PCB Manufacturing

To illustrate the effects of PCB variance on a SerDes circuit, an example transmission line with specific characteristics will be examined. The line in this example will be a Stripline with a .005-in. trace width on ½ oz. copper and .005-in. spacing between traces. The trace will be embedded in FR-4 with a dielectric constant of 4.3. The line's surfaces are 5 mils from an upper ground plane and 8 mils from a lower ground plane. The transmission line must support a 5 gigabits per second (Gbps) bus speed. The example trace pair is eight inches long. The intended impedance of the transmission line is 50 ohms.

Stripline Dimensions

The ratio of the conductor width to the distance from the power planes plays an important role in controlling impedance. The dielectric constant of the material that separates the trace from the power planes is also an important factor. These dimensions all work together to affect the inductance and capacitance of the trace and, consequently, its overall impedance.

Variation in etching time and amount of etchant applied will affect the width of the trace. The typical tolerance on trace width is +/-10 per cent. For our example, the width (W) can range from .0045-in. to .0055-in.

The processes used for creating the core FR-4 and for pressing the pre-preg layers of FR-4 are also inexact. For the purposes of this example, it is assumed that the core thickness is .005-in. (+/-.001-in.) and that the finished pre-preg thickness is .008-in. (+/- .002-in.).

The thickness of a trace is determined by the weight specification. A ½ oz. copper foil is .000675-in. thick (T) and is rarely specified with a tolerance. The thickness is relatively easy to control. For this example, it is considered constant. The dielectric constant is 4.3 with a tolerance of +/- .1, or a range of 4.2 to 4.4.

Impedance is derived from a formula. Click here to see the calculations in a spreadsheet that can be used to determine impedance on typical transmission lines.

If all specifications are exact, the impedance would be 47.77 ohms or close to the ideal. But the cumulative effects of worst case extremes can result in an impedance range of 63.39 ohms (thick dielectrics, narrow trace, and low dielectric constant) to 36.28 ohms (thin dielectrics, wide trace, and high dielectric constant).

Granted, the distribution of this impedance range between 36.28 ohms and 63.39 ohms is Gaussian, but an impedance range this wide is enough to cause significant variation in reflections and, therefore, losses and distortion at the input of the receiving device. The reflection coefficient for the example Stripline, assuming source and load impedances of 50 ohms and considering no variance from the PCB specifications, is .002281. But for the two worst case extremes, the reflection coefficients are -.09413 and .15889.

In other words, based on PCB variances that are within commonly accepted tolerances, as much as 15 percent of the energy in the signal may never enter the receiver. This is enough to have very noticeable effects on signaling margin.

Trace Surface Finish

This example assumes that the Stripline trace is rectangular. In practice, it is not. Process differences between suppliers, or even between different batches of PCBs from one supplier, can cause significant variations in the shape and smoothness of a trace's cross sectional perimeter.

Some of the process variations that can affect the shape of a trace are overetch/underetch, substrate effects, imaging quality, oxide treatments and microetch oxide alternatives, and foil treatments. Some of these effects can be minor, assuming that the PCB manufacturer has assured that the nominal trace width is within tolerance. However, trace surface roughness is proving to be a significant factor in high-speed transmission lines and this variance may not be detected by common PCB tests.

Surface roughness has both good and bad effects. The surface of metal foil is intentionally made rough so that the metal will have a stronger bond to the dielectric materials during core layer production and during the pressing of core and pre-preg layers. Better bonds provide insurance against delamination of the layers, which can cause fatal (and possibly latent) failures on transmission lines. But increasing surface roughness also increases insertion loss.

Due to the skin effect, current density at higher frequencies is concentrated near the outer edge of a conductor – the higher the frequency, the less the skin depth. At 5GHz, the frequency used in this example, the skin depth is only .92 microns and even less for the harmonics. Surface roughness is measured in microns. Roughness typically measures from 1 micron rms (root-mean-square) to 8 microns rms. When surface roughness exceeds the skin depth, the effects of roughness on characteristic impedance and resistance (per unit length) is more pronounced. As current travels down the length of the trace on the outer shell of the metal, the rough outer surface affects the distance the current travels, which increases the resistance. The rough path of the current also forces many changes in the direction of current flow, which increases the inductance of the trace. This is analogous to driving a car over a mountain range vs. driving it on a flat and straight road. This phenomenon is accentuated for the higher harmonics of the signal. As a result, the shape of the signal will be affected.

If a PCB manufacturer changes its foil type or changes its supplier, or if it changes its own processes for ensuring good adhesion to pre-preg layers, surface roughness can change from batch to batch. Due to the non-uniform nature of surface roughness, the effects are difficult to simulate and measure. Performing BER sampling on PCAs from different lots is a good way to measure the effects of such changes.

Random Variance (Defects)

Defects that can occur during the process of manufacturing a printed circuit board include the following:

• Incompletely plated vias
• Annular ring breakout
• Flaws introduced during the imaging process (pin holes, nicks, cuts)
• Plating thickness variances
• Delamination

These kinds of defects may or may not be detected by electrical tests and visual inspection, but they can affect the performance of transmission lines. In fact, some defects may even pass structural and functional tests after the PCA is assembled.

Another characteristic of random defects is that they may not be detected by testing a sample from a batch of PCBs. A BER test of individual assemblies may be required to ensure proper performance.

Conclusions

BER and margin testing are frequently employed during design validation, but due to the complex instrumentation, setup, and time required to run these tests, these techniques are often not repeated after a product is launched into production.

However, the increased deployment of embedded instrumentation inside chips as well as the emergence of protocol standards and tools for communicating with these instruments are enabling BER and margin tests throughout a product's life cycle, and especially during volume manufacturing.

Don't miss the next issue of Connect where Part 2 of this series will explain some of the solutions that can overcome the problem of manufacturing process variations.

References

High-Speed Digital Design – A Handbook of Black Magic
Howard W. Johnson and Martin Graham

High Speed Serdes Devices and Applications
David Stauffer, Jeanne Trinko Mechler, Michael Sorna, Kent Dramstad, Clarence R. Ogilvie, Amanullah Mohammad, and James Rockrohr

Asymmetric Stripline Impedance Calculator http://www.pcb123.com/help/calculators/asm-strip.html

Effects of Conductor Surface Roughness upon Measured Loss and Extracted Values of PCB Laminate Material Df
Scott Hinaga – Cisco Systems, Inc.

Modeling Frequency Dependent Conductor Losses in Serial Data Channel Interconnects
Printed Circuit Design & Fab – July and August issues from 2007