 Accurate BSDL helps ensure compliant boundary scan inplementation
By Dave Bonnett
Technical Marketing Manager
ASSET InterTech
An accurate BSDL file for a device is critical to the test engineer designing board-level tests, but it also plays a critical role for the chip designer trying to ascertain whether the embedded chip-level boundary scan implementation is compliant with the IEEE 1149.1 standard.
 Inaccuracies in BSDL files are frequently introduced from several sources. Two relatively new services from ASSET, BSDL Validation Service and BSDL Silicon Validation, are available to validate the accuracy of BSDL and make this information more useful.
Automatic JTAG Insertion
The embedded JTAG infrastructure is often added to chip designs by EDA tools that insert the required JTAG facilities as one of the last steps in the chip design process. These same insertion tools then generate test benches that validate the correctness of the chip’s JTAG features. A validated JTAG implementation is required for simulation and chip testing, as well as for generating a BSDL file. This entire process is well defined and in most cases accurate BSDL files and complete test sets are produced.
Unfortunately, the JTAG implementations generated by EDA tools often must be modified manually for specific chip designs or to implement special JTAG features, such as support for new technologies not yet supported by the insertion tools. In recent years, many new technologies have used the JTAG infrastructure as a foundation. These technologies include 1149.4 (analog test), 1149.6 (testing of AC-coupled high-speed interconnects) and 1532 (concurrent in-system programming). When the chip designer is implementing any of these technologies, the BSDL file generated by a EDA tool must be manually modified to support these related technologies. When a BSDL file is manually edited, errors tend to creep in.
In addition, these new technologies also may not be supported by test generation tools. As a result, the JTAG implementation in the chip can not be fully tested in simulation before tape out.
In other cases, chip designers may choose to manually insert JTAG into their designs instead of using a JTAG insertion tool. As with any standard, the IEEE 1149.1 standard is open to interpretation. Chip designers may attempt to “optimize” the chip’s JTAG infrastructure and functionality to save silicon or to reduce the number of pins devoted to JTAG. These designers often do not realize the ramifications their changes will have on the testability of boards where the device is eventually deployed. Manually inserting JTAG means that the BSDL file also must be created manually, as well as any chip-level tests to validate that the device is complaint with the JTAG standard.
The Problem of Manual BSDL Generation
Most chip designers are not experts in board test in general and they are certainly not experts in boundary scan in particular. When the JTAG infrastructure is manually designed into a chip, the resulting implementation is usually not compliant or marginally compliant with IEEE 1149.1.
For example, a number of years ago a designer who was working on a digital signal processor (DSP) chip designed JTAG into the device and used ScanWorks to test the evaluation boards that were built. Not surprisingly, the JTAG features would not work and further investigation showed that the chip designer had implemented the JTAG test access port (TAP) controller as a four-state state machine instead of the 16-state state machine with specific state-to-state transition paths required by the standard. The chip designer believed he would not need most of the states, so he decided to “optimize” the JTAG interface by implementing only four states. Consequently, any board with this particular DSP chip could not be tested by ScanWorks or any other commercial JTAG tool for that matter.
Another example of chip designers taking liberties with the JTAG specification involved a programmable logic device (PLD). Designers decided to implement a feature that required a specific state transition to trigger the programming of their PLDs. This worked well with the PLD supplier’s programming tools, but no commercially available boundary-scan tool supported the state transition path. As a result, these PLDs could not be programmed in-system by any third-party boundary-scan tools. This could have been avoided had the chip designers validated the design with boundary-scan tools before devices were built.
The lessons learned from these kinds of examples is that if JTAG is manually implemented at the chip level, or if manual changes are made to the features added by boundary-scan insertion tools, additional test and BSDL validation tools are needed. The best source for these tools are suppliers of tools that read BSDL files and create simulation patterns based them, or boundary-scan companies like ASSET that supply tools that create the board- and system-level test patterns based on these BSDL files.
Validating BSDL
Today, free tools are available to read a BSDL file, check it for syntax and semantic errors, then use it as the basis for generating Verilog simulation test patterns to be run against the design before IC tape-out. These patterns can also be used for production tests. The result is a theoretically correct implementation of IEEE 1149.1 in an IC. ASSET and Agilent Technologies have teamed up to offer a free web-based service, BSDL Validation Service (www.asset-intertech.com/bsdl_service), that will do just this. This new service replaces and enhances the functionality of an older e-mail based service that had been offered by Agilent.
Validation of correct IEEE 1149.1 test features in simulation is an essential step, but the real test is if the device will work in a board or system test environment with commercially available boundary-scan test tools. The process of validating a BSDL file using tools based on commercially available boundary-scan board test tools not only ensures that the BSDL accurately describes the silicon, but it also, to some extent, validates that the chip’s boundary-scan features are complaint with IEEE 1149.1. This type of service, which ASSET offers as its BSDL Silicon Validation service, verifies that the chip will work with other devices on the JTAG boundary scan path and that the device can be supported by ScanWorks. Because a fixture specific to each device must be built to validate an IC, the BSDL Silicon Validation service requires a nominal fee.
The benefits of greater accuracy in BSDL files will include greater user satisfaction with semiconductor devices because this will enable more effective testing and troubleshooting methods in products, which, in turn, will make these products easier to develop, manufacture, support and maintain.
For more information on ASSET’s BSDL Validation Service, click here for an article from the previous issue of Connect or go directly to the site at www.asset-intertech.com/bsdl_service.
For the page on the ASSET web site that discusses both BSDL Validation Service and BSDL Silicon Validation, click here.
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