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It’s
a given that the buses on a design for a high-speed
processor board must operate at high speeds. When
one doesn’t, there’s a problem.
A design team at Ircona faced such a dilemma. Ircona is a design consultancy firm in West Dublin, Ireland, that specializes in high-speed computer and server designs, and BIOS customization work. In this particular case, the ScanWorks platform for embedded instruments helped the team identify a fault on a high-speed bus and correct it before the board went into manufacturing.
Verifying the operation of high-speed buses has become increasingly difficult for Ircona’s engineers because these buses provide no physical access where an oscilloscope’s probe might be placed to validate the integrity of the signaling. And even if there is access, placing a probe on a high-speed bus would only inject anomalies into the signal. In the end, scopes have to rely on high-order mathematics to simulate – or guess at – what the signaling actually looks like at the receiver.
“And some of these scopes cost more than the design does,” said a frustrated Dan Collins, operations director at Ircona.
In this case, Ircona’s processor board design was optimized for a very high-speed server application. Based on Intel®’s Xeon® 7500 Series processors with the Nehalem microarchitecture, the circuit board featured several high-speed input/output (I/O) buses, including Intel’s QuickPath Interconnect (QPI) and DDR3 memory buses. (See the figure below for a representative block diagram of the Ircona design.) Because of the application, the design deviated well beyond any Intel-published reference design. Many of the traces on the very compact design were buried on one of the inner layers of the board’s 22 layers. And since the circuit board was water-cooled, physical access to the board for a probe was nonexistent.
“We’re finding that oscilloscopes are not the answer anymore,” Collins said. “In addition to having no physical access to the board itself, you’ll get reflections on the line if you place a probe on it. With the ScanWorks platform we were able to see what the die sees.”
A problem with one of the QPI buses on the design only came to light after extensive simulation prior to board layout had failed to alert the design team to a crosstalk condition. In fact, the problem was more difficult to identify than is typically the case. Physical validation tests with ScanWorks showed that the bus in question functioned just fine at slow speeds, but when the speed of the bus was increased, bit error rate (BER) testing detected an unacceptably high number of errors.
“We ran into crosstalk on a QPI bus that was
being caused by another non-QPI bus close by,” Collins
explained. “You really need a tool like ScanWorks
that shows exactly what’s going on physically
on the board. The flexibility and ease-of-use for
a software-based tool like this is essential.”
Limiting the design team to legacy validation and test equipment certainly would have jeopardized the project schedule for Ircona to deliver a completed and working design to its client. Simply setting up the validation tests for an oscilloscope would have involved a lengthy process of determining which subset of all the signals on the design would be examined, re-working a number of prototype boards to solder on access points for probes and then figuring out how to fit the re-worked prototype boards into a breakout fixture for testing. This process can be very challenging. It is not uncommon that the power supply or daughtercards for a re-worked board cannot be attached to the board-under-test when it is placed in the breakout fixture. In many cases like this, access to the topside of a processor chip is often blocked by a heat sink or its clamp. Finally, triggering mechanisms must be devised to ensure that the oscilloscope is gathering the right data and that the engineer has not missed any possible problems. Only days or weeks later when all of this set-up has been completed can signal integrity testing begin.
Even after such an extensive set-up, if an oscilloscope were used to validate signal integrity it would only be simulating the signaling and not really providing empirical data. At data rates in excess of approximately five gigabits per second (Gbps), high-speed buses are extremely sensitive to the capacitive effects of physical probes. That’s why most reference designs provided by chip manufacturers like Intel prohibit test pads or test points on high-speed I/O buses. Placing a probe on a bus introduces anomalies into the signaling. As a result, the scope must attempt to remove the miscreant signals it had introduced. To do this, the scope performs another layer of simulation based on high-order mathematics. In the end, the scope only postulates what the actual eye might look like, but it is still a simulation, not the actual eye.
The non-intrusive nature of the software-driven ScanWorks platform gave the Ircona design team what it needed: fast set-up with no fixtures or rework on the circuit board, and empirical data on the integrity of the signaling at the receiver without simulations or projections.
“With ScanWorks we just connected to the XDP header connector on the board and used the board’s (IEEE 1149.1) boundary-scan infrastructure for access. Then we ran the ScanWorks tools like BER testing and margining,” Collins said. “If we had been using a scope, it would have taken much longer – maybe weeks – and it would not have been nearly so thorough. If we had been using a scope, we could have looked at only a few lanes at a time and we would have been doing multiple tests on multiple boards to see if the signaling degraded. With ScanWorks, we hooked it up, kicked off the tests and came back later that day for the results.”
A major advantage of ScanWorks is its ability to look at the signaling on many lanes or nets at once and then, if a problem is detected, to quickly test individual lanes and nets.
“We found that ScanWorks quickly identified problem areas and we were able to use it to debug and diagnose the cause of the problem within a day usually,” Collins said. “Being able to control individual nets and lanes really helped us debug the board.”
Ircona’s typical design cycle includes a functional simulation of a circuit board design before prototypes are manufactured. The intent is to identify any problem areas and correct them prior to board lay-out beginning. But simulation has its limitations and the design team often must contend with scheduling tradeoffs.
“We simulated this circuit board, but we didn’t see the problem at high speeds on the QPI bus,” Collins explained. “You’re never going to have a simulation that covers 100 percent of the board and you frequently have to decide how much time you can afford to spend on developing the simulation and still make your scheduled completion date.”
Collins estimated that developing a simulation of the entire circuit board in this case could have taken three or four months. “In the end, the customer is putting pressure on you to keep to your schedule and you have to decide what you’re going to simulate and what you’re not going to simulate. And on the first time through with a new and complex design like this, you’re going to have to validate the prototypes. There’s just no way around that.”
That’s just what the design team did and ScanWorks discovered the problem with crosstalk on the QPI bus. A quick re-spin of the design rectified the problem.
With the speeds of I/O buses continuously increasing, Collins and the design teams at Ircona expect that these types of unforeseen surprises will become fairly typical in the future. Intel’s next-generation processors, like Sandy Bridge, as well as the buses themselves, such as PCI Express Generation 3, will certainly exacerbate the situation.
“As everything gets faster on a board design, it gets much tougher to pull data from an oscilloscope,” Collins explained. “There was a time when a scope was the only validation tool we had, but now we need something that is simpler and faster; and the cost of the tool is not so outrageously high. We need a tool that provides us better productivity, not less. We found such a tool in the ScanWorks platform.”
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